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The Panasonic Electric Works' Grid Eye is a thermopile-type infrared sensor with digital communication. Using advanced MEMS technology, the Grid Eye monitors the quantity of infrared rays for 64 pixels of data. This page describes the internal memory structure that can be accessed through an I2C interface.  This information was sourced from the GridEYE datasheet.

Table of Contents

 

I2C Slave Address

 

There are two I2C addresses available for the Grid Eye. The Grid Eye address can be selected by connecting the AD_SELECT terminal to GND or with a 10k Ω pull-up resistor to VDD.

 

GND

0b1101000

Pull-up to VDD

0b1101001

Power Control Register

 

The Grid Eye has four modes of operation.  The operations include normal, sleep, and two types of stand-by. These modes can be selected by writing to this register. The current mode of operation can also be read from this register. This register is at address 0x00.

 

Bits

Result

0b00000000

Normal Mode

0b00010000

Sleep Mode

0b00100000

Stand-by with 60 second interference

0b00100001

Stand-by with 10 second interference

 

 

0x00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

Reset Register

 

The Reset Register is used for two operations: full software reset and flag reset. This register is write-only and a full byte wide starting at address 0x01.

 

Bits

Result

0b00110000

Flag Reset

0b00111111

Software Reset

 

 

0x01

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

Frame Rate


The frame rate of the Grid Eye can be set and read from the register at address 0x02. The ability to select between 1 FPS and 10 FPS are available. The default value is 10 frames per second.

 

Bit 0

Result

0

10 FPS (default)

1

1 FPS

 

 

0x02

-

-

-

-

-

-

-

Bit 0

 

Interrupt Setup

Interrupts can be setup internally inside of the Grid Eye. When a single pixel passes a given value, an interrupt will occur. When an interrupt occurs, the interrupt flag in the Status Register is set high. Additionally, the INT pin of the Grid Eye can be setup to be pulled low when an interrupt occurs. This register is both readable and writable and is at address 0x03. See the Interrupt Level Register to set the trip values for the interrupt.

 

Bit 0

Result

0

INT Pin reactive (High Impedance) (default)

1

INT Pin Enable

Bit 1

Result

0

Difference Mode (default)

1

Absolute Mode

 

 

0x03

-

-

-

-

-

-

Bit 1

Bit 0

 

Status Register

The Status Register contains flags on the thermistor temperature output overflow, temperature output overflow, and pixel interrupt. The address for the Status Register is 0x04. The flags can be reset by writing to the Status Clear Register.

 

Bit 1

Result

0

No Interrupt

1

Interrupt Occurred

Bit 2

Result

0

Temperature Output OK

1

Temperature Output Overflow

Bit 3

Result

0

Thermistor Temperature OK

1

Thermistor Temperature Overflow

 

 

0x04

-

-

-

-

Bit 3

Bit 2

Bit 1

-

 

Status Clear Register

The flags in the Status Register can be reset by writing to the Status Clear Register. This register is designed to only be written to. After writes occur to this register, the value of each flag reset bit is set to zero.

 

Bit 1

Result

0

Don’t Reset Interrupt Flag

1

Reset Interrupt Flag

Bit 2

Result

0

Don’t Reset Temperature Output Overflow Flag

1

Reset Temperature Output Overflow Flag

Bit 3

Result

0

Don’t Reset Thermistor Temperature Flag

1

Reset Thermistor Temperature Overflow Flag

 

 

0x05

-

-

-

-

Bit 3

Bit 2

Bit 1

-

 

Average Register

This register is used for the moving average output. This register is currently known to be read-only although some documentation shows this register as writable.

 

Bit 5

Result

1

Twice moving average

 

 

0x07

-

-

Bit 5

-

-

-

-

-

 

Interrupt Level Register

This register sets the interrupt trip values. Both lower limit, upper limit, and the hysteresis level can be set and read between the addresses 0x08 to 0x0D. Interrupt level setting is done using two’s complement. Initially the register is filled with zeroes.

 

0x08

Upper Limit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x09

-

-

-

-

Bit 11

Bit 10

Bit 9

Bit 8

0x0A

Lower Limit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0B

-

-

-

-

Bit 11

Bit 10

Bit 9

Bit 8

0x0C

Hysteresis Level

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0D

-

-

-

-

Bit 11

Bit 10

Bit 9

Bit 8

 

Thermistor

 

Thermistor data is stored in addresses 0x0E and 0x0F. This value is the temperature as seen on the Grid Eye module. This value is very useful in filtering out background noise from the raw pixel values. The resolution of the thermistor data is 0.0625°C.  This register is read-only.

 

0x0E

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0F

-

-

-

-

+ / -

Bit 10

Bit 9

Bit 8

 

Interrupt Table Register

 

When an interrupt occurs due to the pixel temperature, the pixel that caused the interrupt is flagged in this register.

 

Bit

Result

0

Flag was not set

1

Flag was set for this pixel

 

 

0x10

Pix 7

Pix 6

Pix 5

Pix 4

Pix 3

Pix 2

Pix 1

Pix 0

0x11

Pix 15

Pix 4

Pix 13

Pix 12

Pix 11

Pix 10

Pix 9

Pix 8

0x12

Pix 23

Pix 22

Pix 21

Pix 20

Pix 19

Pix 18

Pix 17

Pix 16

0x13

Pix 31

Pix 30

Pix 29

Pix 28

Pix 27

Pix 26

Pix 25

Pix 24

0x14

Pix 39

Pix 38

Pix 37

Pix 36

Pix 35

Pix 34

Pix 33

Pix 32

0x15

Pix 47

Pix 46

Pix 45

Pix 44

Pix 43

Pix 42

Pix 41

Pix 40

0x16

Pix 55

Pix 54

Pix 53

Pix 52

Pix 51

Pix 50

Pix 49

Pix 48

0x17

Pix 63

Pix 62

Pix 61

Pix 60

Pix 59

Pix 58

Pix 57

Pix 56

Pixel Data

 

The raw values are stored in the Grid Eye register starting at address 0x80 and continuing through bit 0xFF. The data can only be read. When updating, the Grid Eye updates all of the pixel data at once. This prevents any stale data from being collected during a read.

 

Pixel 0

0x80

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x81

-

-

-

-

+ / -

Bit 10

Bit 9

Bit 8

 

- Pixels 1 through 62 -

 

Pixel 63

0xFE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0xFF

-

-

-

-

+ / -

Bit 10

Bit 9

Bit 8

 

The following shows how the pixels are identified within the Grid Eye.

 

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

 

Full Register Map


Address

Read/Write

Description

0x00R/WOperating Mode
0x01WSoftware Reset
0x02R/WFrame Rate
0x03R/WInterrupt Function
0x04RInterrupt Flag
0x05WInterrupt Flag Clear
0x06--
0x07RMoving Average Output Mode
0x08R/WUpper Interrupt Value
0x09R/WUpper Interrupt Value
0x0AR/WLower Interrupt Value
0x0BR/WLower Interrupt Value
0x0CR/WHysteresis Interrupt Value
0x0DR/WHysteresis Interrupt Value
0x0ERThermistor Output Value
0x0FRThermistor Output Value
0x10RPixel 0-7 Interrupt Flag
0x11RPixel 8-15 Interrupt Flag
0x12RPixel 16-23 Interrupt Flag
0x13RPixel 24-31 Interrupt Flag
0x14RPixel 32-39 Interrupt Flag
0x15RPixel 40-47 Interrupt Flag
0x16RPixel 48-55 Interrupt Flag
0x17RPixel 56-63 Interrupt Flag
0x18--
...--
0x7F--
0x80RPixel 0 Output Value (low)
0x81RPixel 0 Output Value (high)
0x82RPixel 1 Output Value (low)
0x83RPixel 1 Output Value (high)
0x84RPixel 2 Output Value (low)
0x85RPixel 2 Output Value (high)
0x86RPixel 3 Output Value (low)
0x87RPixel 3 Output Value (high)
0x88RPixel 4 Output Value (low)
0x89RPixel 4 Output Value (high)
0x8ARPixel 5 Output Value (low)
0x8BRPixel 5 Output Value (high)
0x8CRPixel 6 Output Value (low)
0x8DRPixel 6 Output Value (high)
0x8ERPixel 7 Output Value (low)
0x8FRPixel 7 Output Value (high)
0x90RPixel 8 Output Value (low)
0x91RPixel 8 Output Value (high)
0x92RPixel 9 Output Value (low)
0x93RPixel 9 Output Value (high)
0x94RPixel 10 Output Value (low)
0x95RPixel 10 Output Value (high)
0x96RPixel 11 Output Value (low)
0x97RPixel 11 Output Value (high)
0x98RPixel 12 Output Value (low)
0x99RPixel 12 Output Value (high)
0x9ARPixel 13 Output Value (low)
0x9BRPixel 13 Output Value (high)
0x9CRPixel 14 Output Value (low)
0x9DRPixel 14 Output Value (high)
0x9ERPixel 15 Output Value (low)
0x9FRPixel 15 Output Value (high)
0xA0RPixel 16 Output Value (low)
0xA1RPixel 16 Output Value (high)
0xA2RPixel 17 Output Value (low)
0xA3RPixel 17 Output Value (high)
0xA4RPixel 18 Output Value (low)
0xA5RPixel 18 Output Value (high)
0xA6RPixel 19 Output Value (low)
0xA7RPixel 19 Output Value (high)
0xA8RPixel 20 Output Value (low)
0xA9RPixel 20 Output Value (high)
0xAARPixel 21 Output Value (low)
0xABRPixel 21 Output Value (high)
0xACRPixel 22 Output Value (low)
0xADRPixel 22 Output Value (high)
0xAERPixel 23 Output Value (low)
0xAFRPixel 23 Output Value (high)
0xB0RPixel 24 Output Value (low)
0xB1RPixel 24 Output Value (high)
0xB2RPixel 25 Output Value (low)
0xB3RPixel 25 Output Value (high)
0xB4RPixel 26 Output Value (low)
0xB5RPixel 26 Output Value (high)
0xB6RPixel 27 Output Value (low)
0xB7RPixel 27 Output Value (high)
0xB8RPixel 28 Output Value (low)
0xB9RPixel 28 Output Value (high)
0xBARPixel 29 Output Value (low)
0xBBRPixel 29 Output Value (high)
0xBCRPixel 30 Output Value (low)
0xBDRPixel 30 Output Value (high)
0xBERPixel 31 Output Value (low)
0xBFRPixel 31 Output Value (high)
0xC0RPixel 32 Output Value (low)
0xC1RPixel 32 Output Value (high)
0xC2RPixel 33 Output Value (low)
0xC3RPixel 33 Output Value (high)
0xC4RPixel 34 Output Value (low)
0xC5RPixel 34 Output Value (high)
0xC6RPixel 35 Output Value (low)
0xC7RPixel 35 Output Value (high)
0xC8RPixel 36 Output Value (low)
0xC9RPixel 36 Output Value (high)
0xCARPixel 37 Output Value (low)
0xCBRPixel 37 Output Value (high)
0xCCRPixel 38 Output Value (low)
0xCDRPixel 38 Output Value (high)
0xCERPixel 39 Output Value (low)
0xCFRPixel 39 Output Value (high)
0xD0RPixel 40 Output Value (low)
0xD1RPixel 40 Output Value (high)
0xD2RPixel 41 Output Value (low)
0xD3RPixel 41 Output Value (high)
0xD4RPixel 42 Output Value (low)
0xD5RPixel 42 Output Value (high)
0xD6RPixel 43 Output Value (low)
0xD7RPixel 43 Output Value (high)
0xD8RPixel 44 Output Value (low)
0xD9RPixel 44 Output Value (high)
0xDARPixel 45 Output Value (low)
0xDBRPixel 45 Output Value (high)
0xDCRPixel 46 Output Value (low)
0xDDRPixel 46 Output Value (high)
0xDERPixel 47 Output Value (low)
0xDFRPixel 47 Output Value (high)
0xE0RPixel 48 Output Value (low)
0xE1RPixel 48 Output Value (high)
0xE2RPixel 49 Output Value (low)
0xE3RPixel 49 Output Value (high)
0xE4RPixel 50 Output Value (low)
0xE5RPixel 50 Output Value (high)
0xE6RPixel 51 Output Value (low)
0xE7RPixel 51 Output Value (high)
0xE8RPixel 52 Output Value (low)
0xE9RPixel 52 Output Value (high)
0xEARPixel 53 Output Value (low)
0xEBRPixel 53 Output Value (high)
0xECRPixel 54 Output Value (low)
0xEDRPixel 54 Output Value (high)
0xEERPixel 55 Output Value (low)
0xEFRPixel 55 Output Value (high)
0xF0RPixel 56 Output Value (low)
0xF1RPixel 56 Output Value (high)
0xF2RPixel 57 Output Value (low)
0xF3RPixel 57 Output Value (high)
0xF4RPixel 58 Output Value (low)
0xF5RPixel 58 Output Value (high)
0xF6RPixel 59 Output Value (low)
0xF7RPixel 59 Output Value (high)
0xF8RPixel 60 Output Value (low)
0xF9RPixel 60 Output Value (high)
0xFARPixel 61 Output Value (low)
0xFBRPixel 61 Output Value (high)
0xFCRPixel 62 Output Value (low)
0xFDRPixel 62 Output Value (high)
0xFERPixel 63 Output Value (low)
0xFFRPixel 63 Output Value (high)

Relevant Products

 

Panasonic Electric Works Part Number

Digi-Key Part Number

Packaging

Description

 
 

AMG8831

255-3509-2-ND

Tape & Reel

Grid-EYE, 3.3 V, High gain

 

255-3509-1-ND

Cut Tape

 

255-3509-6-ND

Digi-Reel®

 

AMG8832

255-3506-2-ND

Tape & Reel

Grid-EYE, 3.3 V, Low gain

 

255-3506-1-ND

Cut Tape

 

255-3506-6-ND

Digi-Reel®

 

AMG8851

255-3507-2-ND

Tape & Reel

Grid-EYE, 5.0 V, High gain

 

255-3507-1-ND

Cut Tape

 

255-3507-6-ND

Digi-Reel®

 

AMG8852

255-3508-2-ND

Tape & Reel

Grid-EYE, 5.0 V, Low gain

 

255-3508-1-ND

Cut Tape

 

255-3508-6-ND

Digi-Reel®

 

 

Additional Information

Panasonic Grid Eye Breakout Board and GUI

Panasonic Grid Eye Library for Atmel Software Framework

 

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