Version 2.0: tmds_encoder.vhd
Corrected bug in the control signals
Version 1.0: no longer available
- VHDL source code of a transition-minimized differential signaling (TMDS) encoder
- 8b/10b encoder compliant with the Digital Visual Interface (DVI) Specification, Section 3.2
This details a TMDS encoder component, written in VHDL for use in CPLDs and FPGAs. The component reads data and control signals from user logic over a parallel interface, performs the encoding algorithm, and outputs the result in a parallel fashion. It was designed using Quartus II, version 13.1. Figure 1 illustrates a typical example of the TMDS encoder integrated into a system.
Figure 1. Example Implementation
TMDS is a method for serially transmitting high-speed digital signals. The “transition minimized” part is realized by the 8b/10b encoding algorithm used by TMDS, which is implemented here in digital logic. This TMDS encoding is used in several digital communication interfaces, including the DVI and HDMI video interfaces. It is important to note that this TMDS encoding was created by Silicon Image in 1999 and is not the same as the original 8b/10b encoding introduced by IBM in 1983. The “differential signaling” part of the technique relates to the IO circuit and is not discussed in detail here.
The TMDS encoding algorithm reduces electromagnetic emissions, achieves DC balance on the wires, and still allows for reliable clock recovery. The encoding seeks to minimize the transitions (thus reducing interference between channels) while still retaining frequent enough transitions for clock recovery. By keeping the number of ones and zeros on the line nearly equal, the DC balance part of the encoding algorithm improves the noise margin.
Figure 2 shows the TMDS encoding algorithm.
Figure 2. Encoding Algorithm
For more information, see the DVI specification attached below in the “Additional Information” section. It explains the entire TMDS technology in detail.
Table 1 describes the TMDS encoder’s ports.
|clk||1||in||standard logic||user logic||System clock.|
|disp_ena||1||in||standard logic||user logic||0: outputs control word based on the control input|
1: outputs encoded 10-bit data based on 8-bit data input
|control||2||in||standard logic vector||user logic||MSB is control bit C1, and LSB is control bit C0|
|d_in||8||in||standard logic vector||user logic||8-bit data to be encoded|
|q_out||10||out||standard logic vector||user logic||10-bit encoded output|
This TMDS encoder is a programmable logic component that implements the 8b/10b encoding algorithm required by the DVI and HDMI video interfaces.
Comments, feedback, and questions can be sent to firstname.lastname@example.org.